Pulse-count control circuit wherein the input is sampled and inhibited upon input exceeding predetermined frequency



June 1, 1965 T.' CASE 3,187,202

PULSE-COUNT CONTROL CIRCUIT WHEREIN THE INPUT IS SAMPLED AND I INHIBITED upon INPUT EXCEEDING PREDETERMI'NED FREQUENCY Filed Oct. 25', 1962 2 Sheets-Sheet 1 mom/as CASE ATTORNEY June I, 1965 T. CASE 3,187,202

PULSE-COUNT CONTROL CIRCUIT WHEREIN THE INPUT IS SAMPLED AND INHIBITED UPON INPUT EXCEEDING PREDE'I'ERMINED FREQUENCY Filed ogt. 25, 1962 2 Sheets-Sheet 2 m/ ur A I I I I I I I I BJIIII I I III wcjl'l I I! H I I III!" mrAJl'l "l-lllll BL] oar-porcLI I INVEN TOR.

THO/7A5 CA 56 BY 2 Z;

A TTORNEY 3,181,202 Patented June 1,- 1965 3,187,202 PULSE- DUNE CONTRGL CIRCUIT REIN Tim INPUT IS SAMPLEDAND INPUT EXCEEDING PREDE QUENCY Thomas Case, Yonkers, N.Y., assignor to International Telephone and Telegraph corporation of Maryland Filed Oct. 25, 1962, Ser. No. 232,957 9 Claims. (CL 307-835) This invention relates to pulse counting circuits and more particularly to a pulse count control circuit for limiting the pulse density.

In transponders, such as are used in aircraft for airto-air navigation information, pulses received by the aircraft from other aircraft are used to trigger the modulator to transmit reply pulses. The modulators are designed to operate at a certain pulse density or pulse frequency and if this pulse density is exceeded as may occur when a large number of aircraft'are simultaneously transmitting pulses, then the modulator is overloaded and will cause failure of the transmitter. It is therefore desirable and necessary to provide a circuit for limiting the pulse density of received pulses to the pulse forming "circuit of the modulator.

An object of this invention is therefore'to provide a pulse count control circuit which will limit the pulse input to a desired amount.

Another object 'is to provide a pulse count control circuit which will average out the number of pulses over a period of time so that the pulse density will not exceed a desired limit.

A feature of this invention is a pulse count control circuit which is responsive to a source of pulses and in-.

cludes means to sample the pulses and to set a reference pulse count rate level. If the reference pulse count rate level is exceeded, a control pulse is generated which initiates a gate and this gate permits a control pulse to inhibit the .pulse input during a predetermined time interval.

Another feature of this invention is that the gate circuit is a monostable circuit which will provide a gate for a predetermined time during which the pulse input will be inhibited.

The above-mentioned and other features and objects of this invention will become more apparent by reference to the following description taken in conjunction with the accompanying drawings, in which: I

FIGURE 1 is a schematic diagram of the pulse count control circuit of this invention;

FIGURE 2 is a graph of the desired characteristic of the pulse count control circuit or" this invention; and

FIGURES 3 and 4 are waveforms useful in explaining the theory and operation of this invention.

With reference to the figures, there is shown in the schematic diagram a source of pulses 1 coupled by a resistor 2 to the base 3 of a first transistor 4. The normal output pulses appearing at the emitter 5 oftransistor l are also the same pulses to be controlled. These pulses are fed to a two diode pulse sampling circuit which comprises diodes 6 and 7 in series, capacitor 8, which couples the input pulses to the junction of the diodes 6 and 7, capacitor .9 and resistor 10 in parallel which couple the cathode of diode 7 to ground. It also comprises a'couutdown adjustment potentiometer ill, the wiper of which is coupledto the anode of diode 6, and resistor 12 which couples oneend of the potentiometer to a source of voltage. The operation of this portion. of the circuitry is as follows. We assume that initially no charge exists on either capacitor 8 or 9. When the first pulse appears at the emitter junction 5 of transistor 4, it will cause capacitor 8 to be Corporation, Nutiey, N.-J., a

charged through the diode 6. For proper operation, the time constant of capacitor Stimes the total series resistance consisting of the diode 6 forwardflresistance, the emitter follower 5. generator impedance and the Thevenin equivalent resistance of resistor 12 and potentiometer 11 must be small in comparison with the pulse width of the During the time that capacitor 8 is still be-' input pulse. ing charged by the input pulse, the diode 7 is back biased and hence, cannot conduct; thus, the capacitor 9 at the moment remains without a charge on it. At the termination of the input pulse, however, capacitor 8 is left with a net charge which now appears across the diode 7 and the capacitor 9. At this time, the diode 6 is held back biased so that the capacitor 8 will discharge through the diode 7 into capacitor 9. Equilibrium is reached when the two capacitor voltages are equal. The time during which this transfer of energy takes place from capacitors 8 into capacitor 9 must be small compared with the input pulse spacing in order to again allow equilibrium to be established. In order to have proper pulse sampling characteristics, capacitor 9 must act as a long term storage element and hence, must be larger in value than capacitor 8. Therefore, the voltage change across capacitor 9 willbe small compared to the value of the input pulse developed across the capacitor 8. The next pulse that follows will restore the charge oncapacitor 8 and on the termination into capacitor 9. Thus, capacitor 9 will receive another charge on it for each input pulse till it reaches the voltage level at which firing of the next stage occurs if the pulse input exceeds the pulse count rate level. build-up across capacitor 9 is fed to a unijunction transistor 13. The operation of the unijunction pends upon its intrinsic standoff voltage ratio which is a function of the ratio of its internal base 14 resistance to its internal base 15 resistance. If the value of voltage on capacitor 9 is below the intrinsic stand'ofl? voltage threshold value, then unijunction transistor 13 remains in a quiescent 01f state. As soon as a charge on capacitor 9 equals or exceeds this threshold point, the unijunction transistor input emitter to base 15 junction breaks down allowing capacitor 9 to discharge through Q2 emitter to base 15 junction into resistor 16. This rapid discharge of capacitor 9 causes a positive high current pulse to be developed across resistor 16. Resistor 17 appearing in the base 14 lead of the unijunction transistor 13 is'required for temperature compensation of the unijunction transistor 13 internal parameters. developed across resistor 16 is used to initiate the positive gate approximatelylS milliseconds in duration which is a gate voltage signal used for feedback control. The operation of the monostable circuit which makes this 15 millisecond gate will now be explained. t

The components, capacitor 18, diode 19 and resistor 20 provide a means for triggering the monostable multivibrator which comprises transistor 21 and transistor 22 with the associated circuitry to be described. Normally, transistor 22-is conducting and transistor 21' is non-conducting. The current supplied by resistor 23 is divided between two elements, resist'or'24 and the base 25 of transistor 22. Resistor 23 to keep-transistor 22 in its normally on state; In this state, the base 25 of transistor 22 is approximately +0.7

of this pulse, will again discharge through diode '7" The voltage transistor de- The positive pulse just.

supplies the necessary current.

the voltage division shape and unijunction transistor I v 21 in high temperature operation. Whenever a pulse appears across resistor 16, it is coupled to capacitor 18 into the base 28 of transistor 21 turning that transistor on. This causes the collector 31 of transistor 21 to fall from approximately plus 22 volts D.C. to approximately ground level. through capacitor 32 over to the base 25 of transistor 22 turning it off. At this instant, the collector 33 of transistor 22 jumps to approximately 22 volts D.C. and remains at this level for its timing period 15 milliseconds which is determined primarily by the valueof resistor 23 and capacitor 32. This gate, approximately 15 milliseconds in width, is the actual control gate which is fed to the control switch. transistor 35. The operation of transistor 33 is basically that of an on and off switch. This 15 millisecond gate supplies a current through resistor 34 which turns transistor 35 on, saturating it for 15 milliseconds. With transistor 35 in saturation, an effective short circuit is placed between the point B at the base 3 of transistor 4 and ground through the collector-emitter junction of transistor 35. The normal input pulses which appear at point A, as shown in the wave form graphs, are now shorted out at point B. Emitter follower transistor 4 during this 15 millisecond time interval is also effectively shut off or disconnected from the two diode counter described above. No-output pulses in this time can appear at the emitter of transistor 4, point C on the waveform graph, since point C follows exactly the condition that exists at point B. At the termination of the-l5 millisecond gate, transistor 35 turns off, thus removing the short circuit appearing at point B, the base of transistor 4. Thus, the normal pulses appearingat point A now appear at points B and C. V The two diode pulse sampler is now effectively backin the circuit and the complete cycle repeats.

The desired curve forlimiting the transmitter pulses to some fixed pulse density above some specified repeti- FIG. 2. The broken line represents tion rate is shown in V the curve when the feedback loop is open. The full line represents the desired controlled countdown curve with the feedback loop closed. i i

Since the countdown cycle is presumably set at approxi- V mately 750 pulses per second, if the input pulses appearing' at point A shown in FIGURE 3 remain below this number of pulses per second, then nocountdown control willoccur, and points B and C will thus have the same The charging of capacitor 9, as shown in waveform, D, FIG. 3, is at the same level and no pulse will occur at point E and no gate F will be initiated by the monostable circuit. Ifthe .pulses at point A go'rabove 750 pins. as shown in FIGURE 4, the two diode pulse'sampling circuit will sample this increase in pulse the course of events described above. pling count is equal to or below the pulse count rate level This sudden change of voltage is coupled number and initiate. Ifthe pulse sam-.

cessfully tested. The circuit parameters are as follows:

Cl' Capacitor ;rfarads .003 3 C2 Capacitor do .22 C3 Capacitor do .1 C4- Capacitor [L,Ltf 188 C5 Capacitor farads" .22 CR1 Diode i 1N459 CR2 Diode 1N459 CR3 Diode 1N459 CR4- Diode 1N459 Ql Transistor Type 2Nl893 Q2 Transistor Type 2N49 l Q3 Transistor Type 2N338 Q4- Transistor Type 2N338 Q5 Transistor Type 2N1893 Rl'Resistor ohms 3.3K R2 Resistor do 18K R3 Variable resistor do 10K R4 Resistor do 2.2 R5 Resistor do 250K R6 Resistor -do 470 R7 Resistor do 390 R8 Resistor do 330K R9 Resistor Megohms 2.2 R10 Resistor do 2.2 R11 Resistor ohms 10K R12 Resistor do 10K R13 Resistor do 47K R14 Resistor do 82K R15 Resistor do 15K R16 Resistor Megohm 1 number of pulses as appeared at point A.

of the pulse sampling circuit, then the charge on capacitor 9 caused by a pulse dissipates before the nextpulse arrives and the charge does notexceed the level shown in waveform D, FIG. '3. If the pulse input exceedsthe pulse count rate level, then-the time between pulse's is too short-for the charge on capacitor 9 to completely dissipate and the residual charges caused by the succeeding pulses build up to the voltage level shown in waveform D, F1654, until. the triggering level is reached. As shown in FIGURE 4, pulses at B and C occur at the same rate as. at A up to the point when" the capacitor 9' charges, as shown in waveform D, to'above the threshold point and thena discharge of capacitor. 9; through the B areshut off and no output pulsesoccur at point C.

13 emitter to the base 15 junction While I have described above the principles of my invention in connection with specific apparatus, it is to be clearly understood that this description is made only by way of example and .not as a limitation to the scope of my invention as set forth in the objects thereof and in the accompanying claims. a

I claim:

1. A pulse count control circuit responsive to a source of pulses comprising:

input means, output means coupled to said input means,

means coupled to said input means to sample the pulses,

means coupled to said sampling means to set a reference pulse count rate level,

means coupled to said sampling means and responsive to the pulse input exceeding the reference count rate level to generate a control pulse;

and means coupled to said control pulse generating means and responsive to said control pulse to inhibit the pulse input during a predetermined time interval whereby the pulse output atsaid output means is maintained at a rate not exceeding said reference pulse count rate.

2. A pulse counte control of pulses comprising:

input means,

output means coupled to said input means,

circuit responsive to a source means coupled to said input means to sample the pulse,

frequency,

means coupledto said sampling means to set a reference pulse count rate level,

means coupled'to said sampling means to generate a control pulse when the reference count rate'level is exceeded by said pulse input,

gating means coupled to said pulse generating means and responsive to said control pulse to initiate a gat- 'ing pulse forapredetermined time, and

means coupledto said gating means andresponsive to said gating pulse to inhibit the pulse input during said predetermined time whereby the pulse output at said output, means is maintained ata level not exceeding said reference pulse count rate.

3. A pulse count control circuit responsive to a source of pulses comprising:

input means,

output means coupled to said input means,

means coupled to said input means to sample the pulse frequency,

means coupled to said sampling means to set a reference pulse count rate level,

means coupled to said sampling means to generate a control pulse when the reference pulse count rate level is exceeded by said pulse input,

a monostable circuit coupled to said generating means and responsive to said control pulse to initiate a gating pulse for a predetermined time, and

means coupled to said monostable circuit and responsive to said gating pulse to inhibit the pulse input during said predetermined time whereby the pulse output at said output means is maintained at a level not exceeding said reference pulse count rate.

4. A pulse count control circuit responsive to a source of pulses comprising:

input means,

output means coupled to said input means,

means coupled to said input means to sample the pulse frequency,

means coupled to said sampling means to set a reference pulse count rate level,

means coupled to said sampling means to generate a control pulse when the reference pulse count rate level is exceeded by said pulse input,

a gate circuit coupled to said generating means and responsive to said control pulse to initiate a gate for a predetermined time, and

a feedback circut coupled to said gate circuit and responsive to said gate to inhibit the pulse input during said predetermined time whereby the pulse output at said output means is maintained at a level not exceeding said reference pulse count rate.

5. A pulse count control circuit responsive to a source of pulses comprising:

input means,

output means coupled to said input means,

means coupled to said input means to sample the pulse frequency, the time constants of said sampling means determining a reference pulse count rate level,

means coupled to said sampling means to generate a control pulse when the reference pulse count rate is exceeded by said pulse input,

a gating circuit coupled to said generating means responsive to said control pulse to initiate a predetermined time,

and a feedback circuit coupled to said gating circuit and responsive to said gating pulse to inhibit the pulse input during said predetermined time whereby the pulse output at said output means is maintained at a level not exceeding said reference pulse count rate.

6. A pulse count control circuit responsive to a source of pulses comprising:

input means,

output means coupled to said input means,

means coupled to said input means to sample the pulse frequency,

said sampling means including first and second diodes coupled in series, and impedance means coupled to said first and second diodes, said sampling means having a time constant which determines the reference pulse count rate level,

means coupled to said sampling means to generate a control pulse when the reference pulse count rate level is exceeded,

a gate for gating means coupled to said generating means and responsive to said control pulse to initiate a gate for a predetermined time, and

a feedback circuit coupled to said gating means and responsive to the duration of said gate to inhibit the pulse input during said predetermined time whereby 8. A pulse count control circuit according to claim 7 wherein said feedback circuit includes a transistor coupled to the input of said pulse control circuit and said transistor is placed in the conducting state during the duration of said gate to inhibit the pulse input to said circuit.

9. A pulse count control circuit responsive to a source of pulses comprising a first transistor,

means coupling said transistor,

a pulse sampling circuit including first and second diodes coupled in series,

a variable resistor coupled to said first diode and a first resistor and a first capacitor coupling the cathode of said second diode to ground, the constants of said sampling circuit determining a reference pulse count rate, whereby when the input pulses exceed said reference pulse count rate the charge on said first capacitor exceeds a predetermined level,

a second capacitor coupling the emitter of said first transistor to the junction of said first and second diodes,

means coupling the output of said pulse count control circuit to the emitter of said first transistor,

a second transistor,

means coupling the output of said pulse sampling means to the input emitter of said second transistor when the charge on said first capacitor exceeds the predetermined level,

a gating circuit comprising third and fourth transistors,

means coupling the output of the anode of said second transistor to the base of said third transistor,

means coupling the base of said third transistor to the collector of said fourth transistor,

means coupling the collector of said third transistor to the base of said fourth transistor,

a fifth transistor,

means coupling the collector of said fourth transistor to the base of said fifth transistor,

means coupling the collector of said fifth transistor to the base of said first transistor, and

means coupling the emitter of said fifth transistor to ground 'whereby when said fifth transistor is placed in the conducting state in response to an output from said gating circuit said first transistor is placed in a non-conducting state during the duration of the pulse source to the base of said gate and no output is derived from the pulse count control circuit.

References Cited by the Examiner UNITED STATES PATENTS 3,149,243 *9/64 Garfield n 30788.5

Y ARTHUR GAUSS, Primary Examiner. 

1. A PULSE COUNT CONTROL CIRCUIT RESPONSIVE TO A SOURCE OF PULSES COMPRISING: INPUT MEANS, OUTPUT MEANS COUPLED TO SAID INPUT MEANS, MEANS COUPLED TO SAID INPUT MEANS TO SAMPLE THE PULSES, MEANS COUPLED TO SAID SAMPLING MEANS TO SET A REFERENCE PULSE COUNT RATE LEVEL, MEANS COUPLED TO SAID SAMPLING MEANS AND RESPONSIVE TO THE PULSE INPUT EXCEEDING THE REFERENCE COUNT RATE LEVEL TO GENERATE A CONTROL PULSE; AND MEANS COUPLED TO SAID CONTROL PULSE GENERATING MEANS AND RESPONSIVE TO SAID CONTROL PULSE TO INHIBIT THE INPULSE INPUT DURING A PREDETERMINED TIME INTERVAL WHEREBY THE PULSE OUTPUT AT SAID OUTPUT MEANS IS MAINTAINED AT A RATE NOT EXCEEDING SAID REFERENCE PULSE COUNT RATE. 